/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off UNDRIVEN */
`include "defines.svh"
`include "axi_defines.svh"
`default_nettype wire

module axi_fetch(
    input clk,
    input reset,

    input inst_sram_en,
    input addr_t debug_inst_pc,
    input addr_t inst_sram_addr,
    output data_t inst_sram_rdata,
    
    output logic axi_inst_flushreq,
    output addr_t debug_pc,
    
    //R
    output logic  arvalid,
    output addr_t araddr,
    input  logic  arready,

    output logic  rready,
    input  data_t rdata,
    input resp_t rresp,
    input  logic  rvalid
);

    // signal
    rstate_t rstate;
    logic ar_shake,r_shake,aw_shake,w_shake,b_shake;
    
    assign ar_shake = arready && arvalid;
    assign r_shake = rready && rvalid;
    // R
    always_ff @(posedge clk) begin
        if (reset) begin
            rstate <= S_IDLE;
        end else if(rstate == S_IDLE) begin
            if(inst_sram_en) begin
                araddr <= inst_sram_addr;
                rstate  <= AR_WAIT;
                debug_pc <= debug_inst_pc;
                arvalid <= `ON;
            end
        end else if(rstate == AR_WAIT) begin
            if(ar_shake) begin
                rstate <= R_RECV;
                rready <= `ON;
                arvalid <= `OFF;
            end
        end else if(rstate == R_RECV) begin
            if(r_shake) begin
                rready <= `OFF;
                rstate <= S_IDLE;
            end
        end
    end

    resp_t resp_r;
    always_comb begin
        inst_sram_rdata = rdata;
        resp_r = rresp;
        axi_inst_flushreq = inst_sram_en && ~(rstate != S_IDLE && r_shake);
    end
    

endmodule
